By way of background, “Joule heating” results from a current flow encountering resistance in an electrically conductive structure, such as a metal interconnect line in a semiconductor device. As a result of heat caused by Joule heating, the performance of the semiconductor device can be adversely affected. For example, Joule heating could lead to severe interconnect electromigration and/or stress-induced void malfunctions of the semiconductor device.
One approach that has been tried for reducing such malfunctions involves limiting certain operational conditions of the semiconductor device so that such a device is likely to meet specified reliability requirements. For example, one may a priori impose direct current (DC) limits on DC current carrying interconnects to reduce electromigration.
It has been observed that in operational semiconductor devices significant Joule heating can occur due to alternating current (AC) signals that, for example, may be present in the proximity of DC current carrying interconnects, with concomitant large temperature increases in their immediate vicinity. This highly localized temperature increase can affect the operational reliability of the interconnect lines and lead to unforeseen malfunctions. These temperature increases can be well above the device operating range and lead to an unacceptable number of reliability failures and a reduced lifetime. Moreover, these local temperature changes can affect the interconnect stress state, thus altering the electromechanical reliability of the device.
Some known techniques that have been attempted for determining Joule heating effects in wafers or semiconductor devices include the following:                (a) Techniques based on a Temperature Coefficient of Resistance (TCR) estimation for the interconnect lines and temperature estimation under thermal equilibrium conditions. However, instabilities and/or non-uniformities across the wafer may lead to inaccurate temperature estimates for interconnect lines at sub-micron levels, as may be the case in a semiconductor device that comprises a plurality of layers.        (b) Techniques based on infra-red (IR) temperature sensing devices. In practice, however, IR sensing may be somewhat limited since generally just the exposed surface of the die or package is visible to the IR sensing device. Thus, this technique may not offer an accurate estimate of interconnect temperatures at lower layers of a multi-layer semiconductor device.        (c) Stress measurement techniques using thin films deposited on blanket wafers. This technique of stress measurements using blanket wafers, however, may not accurately replicate true stress scenarios in a patterned semiconductor chip or wafer. Moreover, stress measurement techniques using micro-x-ray grid patterns on relatively large area designs (e.g., mm2 size) are not desirable since stress conditions can vary significantly as a function of temperature and Joule heating, thus affecting the ability to obtain an accurate knowledge of interconnect reliability.        
In view of the foregoing considerations, it would be desirable to provide test structures in a test semiconductor device that allow for accurately and consistently determining Joule heating effects, and attendant reliability implications for a class of semiconductor devices built like the test semiconductor device. It is also desirable to provide techniques for performing accurate interconnect temperature measurements that can lead to a more thorough understanding of the true operational capabilities of a semiconductor device.